On-chip random access memories (RAM) have become an essential part of high speed microcomputers. Nonvolatile static type of RAMs are a favored choice of memories for use with microcomputers, as such memories require neither refresh cycles nor corresponding refresh circuitry. U.S. Pat. No. 4,506,322, by Leigh, illustrates a six-transistor memory adapted for use with a high speed microcomputer. However, standard six-transistor or even four-transistor static memories require a substantial amount of wafer area, thereby limiting microcomputer chip designs with respect to on-chip memory capacity.
The dynamic type of random access memories can have as few as one integrated transistor and one capacitor component, and thus a large number of such cells can be fabricated in a small wafer area. However, the dynamic type of random access memories is volatile, in that the stored charge on the capacitor is required to be periodically refreshed, thereby requiring, in many instances, refresh circuitry. On the other hand, the memory refresh requirements may be left to the programmer of the microcomputer to assure that all cells have been accessed in a prescribed period of time.
In high-speed microcomputer applications which are computational intensive, such as in digital signal processing, a large amount of on-chip memory is required. "Cycle stealing" techniques commonly employed by programmers for memory refresh purposes are thus limited. Also, dynamic RAM memories are not easily integrated with microcomputers requiring read and write operations of different addresses within a single machine cycle. Typically, a four-phase microcomputer clocking system provides no time slot for refreshing the memory, and thus the burden is placed on the programmer to ensure that the entire memory array is refreshed. As noted, in real time applications, this constraint is highly undesirable.
U.S. Pat. No. 4,447,891 by Kadota discloses a RAM array which permits simultaneous read and write operations of the various cells of the array, independently of each other. The memory cells of the noted patent each comprise a cross-coupled inverter with additional transistors to effect read and write access to the cell. Complementary data lines are also required by the cell. Although the memory array of the noted patent is of the static type which requires no refresh support considerations, each cell comprises a large number of transistors and thus is not well adapted for high density applications.
From the foregoing, it can be seen that a need exists for an improved memory array having dynamic-type cells adapted for high density fabrication, and in which refresh operations are transparent to the programmer or user. A further need exists for a semiconductor memory which is well adapted for use with a four-phase machine cycle where read and write operations of different cells can occur during the same cycle, and where memory refresh operations are automatically undertaken. Yet a further need exists for a memory array having cells with two transistors and a capacitor component, all well adapted for fabrication according to current semiconductor processing techniques.